Fan-out was once regarded as a low-cost IC packaging option and is now becoming mainstream and upstream.
Chip manufacturers, OSATs, and R&D organizations are developing the next wave of fan-out packaging for a range of applications, but it turns out that sorting out new options and finding the right solution is a challenge.
Fan-out is a method of assembling one or more chips in an advanced package, which makes the chips have better performance and more I/O, and is suitable for applications such as computing, Internet of Things, networking and smart phones. In only one example of fan-out, DRAM chips are stacked on logic chips in the package. This in turn brings memory and processing functions closer together, thereby providing more bandwidth to the system.
Fan-out is not the only advanced package type on the market, but it does have some advantages over competing technologies such as 2.5D.
Yole Développement analyst Stefan Chitoraga said: “As part of advanced packaging, fan-out solutions have become critical and effective for improving device performance and bandwidth. According to Yole, overall, the fan-out packaging market is expected to grow from 2020 This year’s 1.475 billion US dollars will increase to 1.953 billion US dollars in 2021.
Figure 1: Different options for high-performance computing packages, interposer-based 2.5D and fan-out chip-on-substrate (FOCoS). Source: ASE
Fan-out packaging is not new. In fact, it has existed since the mid-2000s. But this technology did not receive attention until 2016, when Apple adopted TSMC's fan-out package in the iPhone 7 and subsequent mobile phones. Suddenly, other packaging companies developed a large number of new and different fan-out packages. Today, the list of fan-out types continues to grow, making it difficult to track options and where they fit.
Each version of fan-out has its own set of trade-offs. Fanouts can be developed using different manufacturing processes. They can also be made on round wafers or panels.
Their adoption rate is also growing. Fan-out encapsulation used to compete in a clearly defined space. Nowadays, fan-out packaging is expanding in the mid-range and high-end markets, where it may compete with other forms of advanced packaging.
Semiconductor engineering has studied the latest fan-out technologies in various applications such as computing, mobile, and networking, and the scope of application of these solutions.
Types of packaging For many years, packaging has been an important part of the semiconductor ecosystem. After the chip manufacturer processes the wafer in the fab, the chips on the wafer are cut and integrated into the package. The package encapsulates the chip to prevent it from being damaged. It also provides electrical connections from the device to the circuit board.
There are many types of packaging, each of which is suitable for a specific application. One way to segment the packaging market is through interconnection types, including wire bonding, flip chip, wafer level packaging (WLP), and through silicon via (TSV). Interconnects are used to connect one chip to another chip. TSV has the highest number of I/O, followed by WLP, flip chip and wire bonding.
According to TechSearch International, about 75% to 80% of packages today are based on wire bonding technology, which is an older technology. Wire bonders use thin wires to stitch one chip onto another chip or substrate. Wire bonding is used in low-cost traditional packages, mid-range packages, and memory chip stacking.
Quad Flat No-lead (QFN) and Quad Flat Package (QFP) are two examples of packages based on wire bonding. "We see that the demand for QFN packages is stronger than ever before," said Rosie Medina, vice president of sales and marketing at QP Technologies. "They are used in many end markets, such as medical, commercial, and military/aerospace. Handheld devices, wearable devices, and circuit boards with many components are the main applications."
Flip chip is another interconnect technology used in multiple package types, such as ball grid array (BGA). In flip chip, a large number of tiny copper bumps are formed on the top of the chip. The device is then turned over and mounted on a separate chip or board. The bumps land on the copper pads, forming electrical connections.
WLP is a technology that encapsulates dies in a wafer-like form. Fan-out is considered a WLP technique.
2.5D/3D packages are used in high-end systems. In 2.5D/3D, the dies are stacked or placed side by side on top of the interposer, and the interposer contains TSV. In one example, FPGA and high bandwidth memory (HBM) are placed side by side in a 2.5D package. HBM is the DRAM memory stack.
"Through Silicon Via (TSV) is an enabling technology for 3D-IC because it provides electrical connections between stacked chips. The main advantage of 3D-IC technology with TSV is that it provides a shorter distance between different components. Interconnection, resulting in lower RC delay and smaller device footprint," said Luke Hu, a researcher at UMC, in a paper: the recent IEEE Electronic Components and Technology Conference (ECTC). Others contributed to the work of the paper, which describes the TSV pre-binding certification process.
2.5D/3D, fan-out, and related technologies are considered advanced packaging types designed to solve several problems. For example, in a system, data moves back and forth between a separate processor and an on-board storage device. But sometimes this exchange will cause delays and increase energy consumption. One way to solve the problem is to bring the memory and processor closer together and integrate them into an advanced package.
There are other applications. Traditionally, in order to advance the design, chip manufacturers have developed ASICs. Then, at each node, they integrate more functions on the ASIC. But this method is becoming more and more expensive at each node.
Another way to gain the advantage of scaling is to assemble complex and different chips in new forms of advanced packaging, sometimes called heterogeneous integration.
Fan-out flow At the same time, fan-out appeared in the mid-2000s. At that time, Infineon developed one of the first fan-out technologies. This technology, called Embedded Wafer Level Ball Grid Array (eWLB), is used to install Infineon’s mobile phone baseband chips.
Later, Infineon licensed eWLB technology to three OSATs-ASE, Namium and STATS. (In 2015, JCET acquired STATS, and Amkor acquired Nanium in 2017.)
Over time, packaging companies have developed different types of fan-out besides eWLB. In all cases, fan-out is different from other forms of advanced packaging, namely 2.5D/3D. Fan-out does not require an expensive interposer, so it is cheaper than 2.5D/3D.
Fan-out is also different from traditional packaging. In traditional packaging, the chips on the wafer are cut and then assembled in the package in one form or another.
In contrast, fan-out is of the WLP type, which means that the die is packaged in a wafer-like form. Fan-in packaging, sometimes called chip-scale packaging (CSP), is also a WLP type. "This type of package can create a wafer package that is almost the same size as the original chip," said Sandy Wen, a process integration engineer at Lam Research Coventor. Therefore, WLP-based packages are usually used to save board space in the system.
Both fan-in and fan-out follow the same basic manufacturing process. First, the chips are processed on wafers in the fab. Then, the chips on the wafer are diced. The die is placed in a wafer based on epoxy molding compound. This is called refactoring the wafer.
Then, a redistribution layer (RDL) is formed on the molding compound in the polymer layer. RDL is a copper metal connection trace that electrically connects one part of the package to another. RDL is measured by lines and spacing. Lines and spacing refer to the width and spacing of metal traces.
Once these processes are completed, the individual packages on the reconstituted wafer are cut.
Figure 2: Cross-section of the bottom of the RDL substrate. Source: Amkor
However, fan-in and fan-out are different. In fan-in, the RDL traces are routed inward. As a result, fan-in was limited, and power was exhausted at about 200 I/Os.
In fan-out, RDL traces can be routed in and out, enabling a thinner package with more I/O. "In fan-out, you expand the usable area of the package," said John Hunt, senior director of engineering at ASE. "In general, I/O refers to the connection that brings the signal and/or power and ground connections into or out of the package."
Over the years, fan-out has moved to RDL with finer lines and space. "As system complexity increases and the heterogeneous integration of large, high-I/O chips into one package, the number of redistribution traces required to interconnect them has grown exponentially. In order to physically route all these interconnects Ground is installed in the package, we need to reduce the wiring and space," Hunt said.
Five years ago, fan-out packages consisted of RDL with 12μm lines and 12μm spaces (12μm/12μm). "10μm/10μm is very common now," said Mike Kelly, vice president of advanced packaging development and integration at Amkor. "Today, the mainstream is 2μm/2μm, and it will develop to 1.5μm/1.5μm now and in 2022. 1.5μm/1.5μm will solve 90% of high-density fan-out products in the next three to four years. Starting next year, some refined The leading edge of the selected product will be 1μm/1μm."
Not all fan-outs are the same. Today, there are three manufacturing processes for fan-out-chip first/face down, chip first/face up, and chip after.
eWLB and other types are manufactured using the chip first/face down method. "In this method, a single chip is placed in a heat release adhesive on a temporary carrier. The mold is overmolded on the carrier. The resulting reconstituted plastic wafer with the chip is separated from the carrier, and The RDL is directly connected to the die pad," said Hunt of ASE.
Chip-first die-up is different. "The incoming wafer is first plated with copper pillars on the die pads. Then the die is separated and the die is placed face up in a heat release adhesive on a temporary carrier. The mold is overmolded on the carrier The resulting reconstituted plastic wafer with the die is peeled from the carrier. The RDL is now connected to the exposed copper pillar surface," Hunt said.
Chip-last is another option. First, the RDL is formed on the temporary carrier. “The die is flip-chip connected to the RDL on the carrier and overmolded. The carrier is then released and the final back-end processing is completed,” Hunter said.
There are some challenges. In this process, the reconstructed wafer is prone to warp. Then, when the chips are embedded in the compound, they tend to move, causing an undesirable effect called chip shift. This will affect production.
There are some solutions, at least for warpage. At ECTC, Brewer Science published a paper on a single-layer mechanically peeling adhesive. "The materials proposed in this work can provide several advantages over other material systems, such as 1) ultra-thin wafer processing; 2) high thermal stability; 3) high-stress substrates with low warpage; 4) single coating and Baking to reduce cost of ownership and increase yield, and 5) simple material cleaning,” said Xiao Liu, Senior Project Manager at Brewer Science. Others contributed to this work.
Mobile fan-out Looking forward to the future, vendors continue to develop fan-out, which is divided into two parts-standard density and high density. For mobile and IoT, standard density fan-out is defined as a package with less than 500 I/O and greater than 8μm lines/space. For high-end systems, high-density fan-out has more than 500 I/Os and lines/spaces less than 8μm.
However, things are not that simple. Each supplier may have multiple standard and high-density fan-out options. And each option may have different configurations, package sizes and integration schemes.
A scorecard may be needed to interpret these options. One way to understand the market is to look at some of the main applications that are fan-out, namely smartphones, computing, and the web. Fan-out is also found in automobiles and the Internet of Things.
The smartphone represents an application. For some time, Apple has added fan-out to the iPhone to encapsulate a key device-the application processor. The mobile phone also contains a large number of other chips, all of which require mixed package types.
Not all smart phones include advanced packaging, especially application processors. Today, many mobile phone processors use the traditional flip-chip BGA package. These bags are cheaper and more mature.
Nevertheless, Amkor, ASE, JCET, and TSMC are each developing fan-out packages for the latest smartphones. In the latest example, TSMC has introduced a new mobile fan-out technology called InFO_B. The package is similar to its current InFO package, where DRAM chips are stacked on logic components. In InFO_B, TSMC develops the bottom (logic) of the package. But in a major change, the DRAM stacking or attaching process is performed by a third party, such as OSAT, instead of TSMC.
This allows customers to flexibly integrate DRAM chips from different vendors into the package. "It provides better electrical performance than flip-chip solutions," Jerry Tzou, Director of Advanced Packaging Business Development at TSMC, said in a speech.
Fan-out is also being developed for infrastructure in 5G. Today, operators are deploying 5G networks at frequencies below 6 GHz. Some operators are deploying next-generation 5G networks using 26GHz, 28GHz and 39GHz millimeter wave frequency bands.
The industry is developing new IC packages for 5G millimeter wave. These packages combine radio frequency chips and antennas in the same unit, called packaged antennas (AiP). The idea behind these new integrated antenna solutions is to bring the RF chip closer to the antenna to enhance the signal and minimize losses in the system.
On ECTC, Fraunhofer IZM, Technical University of Berlin and GlobalFoundries described a project that involved the development of millimeter wave 5G modules for small cell base stations. The project involves the development of a dual-molded fan-out package for the rear chip with AiP.
The software package integrates two modules. The bottom module is composed of analog front-end IC, based on GlobalFoundries' 22nm FD-SOI technology. The top module integrates two antennas.
"The target package size is 10 x 10mm², and the integrated antenna array consists of 2 x 2 patch antenna arrays, which can operate in dual bands of 28GHz and 39GHz, and the minimum impedance bandwidth required for both bands is 400MHz," said Tanja Braun, Fraunhofer IZM's group manager, in an ECTC paper.
2.5D At the same time as fan-out, some vendors are developing fan-out for the high-end computing and network markets. In some cases, high-end systems integrate different chips on the board, such as processors, memory, etc. However, placing discrete chips on the board takes up too much space and is inefficient when moving data from one device to another.
This is where 2.5D fits. By putting multiple chips in a 2.5D package, OEMs can implement more functions in a smaller form factor. It enables the chips to be more closely integrated, thereby achieving more memory bandwidth.
2.5D is also designed to handle larger chip architectures. In some cases, the chip architecture consists of multiple dies and cannot be mounted on a single interposer. Two or more interposers may be required to accommodate all the dies.
To develop larger interposers, chip manufacturers use photolithography scanners to pattern multiple interposers on the wafer. The scanner can print features with a field size of 26 mm x 33 mm. The size of this field represents what many people call the marking limit.
Therefore, the reticle size of the interposer is approximately 26mm x 33mm. At the same time, in the fab, the supplier may use two independent interposers and stitch them together to create a larger interposer that can accommodate more dies in a 2.5D package.
All in all, 2.5D is fast and provides more I/O, but it is also very expensive. Therefore, the industry is looking for lower-cost alternatives. Jan Vardaman, President of TechSearch International, said: "We will see more large-area fan-outs for high-performance applications as alternatives to silicon interposers."
Amkor, ASE, TSMC and other companies are dedicated to large-area, high-density fan-out, supporting multiple logic chips and HBM. All of these use standard package sizes.
The fan-out also exceeds the 1X mask size. For example, on ECTC, TSMC published a paper on 2.5x mask size fan-out (2100 mm2) and 110 x 110 mm2 substrate. It has 5 layers of 2μm/2μm RDL.
This package is ideal for network equipment. Usually, network providers will develop large ASICs to handle the switching functions in these systems. But with each generation of ASICs, they are getting bigger and bigger and their costs are getting higher and higher. Therefore, some vendors are breaking down large ASICs into smaller chips and integrating them into one package. Multi-chip modules (MCM) are one option. MCM integrates the chip into the module, and its RDL can be 15μm/15μm.
Fan-out is another option. In a configuration in a network system, TSMC's fan-out package can contain two logic chips and eight I/O chips. The logic die is located in the middle of the package, and there are two I/O dies on each of the four sides.
According to a paper published on ECTC by TSMC researcher YP Chiang, TSMC’s new fan-out package uses a finer-pitch RDL with more I/O, and its performance is 7 times higher than that of MCM.
Others are also developing large-scale fan-outs. The trick is to connect multiple dies in the package without using interposers.
For some time, ASE has been developing a fan-out technology called fan-out chip-on-substrate (FOCoS), including chip-first and chip-final versions.
At ECTC, ASE described a new technology called sFOCoS, which is a fan-out package with a silicon bridge. Basically, a bridge consists of a small piece of silicon chip with a wiring layer, which connects one chip in the package to another chip.
This is not a new concept. Intel has developed a silicon bridge for packaging. Now, Amkor, ASE and TSMC are developing similar technologies.
"The advantage of silicon bridge technology is to provide better scalability and design flexibility to allow high-density chip-to-chip interconnects with a line pitch of less than 1μm X 1μm," said Lihong Cao, ASE's engineering technology marketing director, in the presentation .
In one configuration, ASIC and HBM are stacked side by side in a fan-out package. The ASE bridge is embedded in the package and connects the ASIC to the HBM. The size of the bridge chip is 6mm x 6mm, and the bump pitch is 55μm.
At the same time, Amkor described a bridging/connection technology called S-Connect. "S-Connect technology was developed using multi-chip fan-out interposers with various functions, such as chip-to-chip connections that can integrate passive and active devices," said developer JiHun Lee. Amkor engineer, ECTC.
Amkor's solution has two configurations. The first option is similar to a small, fine-pitch silicon interposer. The second option uses multilayer RDL made in molding compound.
More fan-outs Other types of fan-outs are also underway. For example, A*STAR describes a fan-out package for deep neural networks. The package contains four dies based on 22nm FD-SOI. The chips are connected using Intel's Advanced Interface Bus (AIB), which is a chip-to-chip PHY-level standard.
Then, ECTC, JCET and Wingcomm describe a sealed eWLB technology for fiber optic communication (FOC) applications. The package contains two FOC devices, including a 25Gb/s optical receiver/transmitter and a 100Gb/s four-channel transmitter.
The conclusion is obviously that fan-out is an enabling technology. It provides customers with new packaging options.
With the popularity of this packaging method, more options are expected over time. But organizing these and integrating them is not simple, even for the most complex design teams.
The next wave of advanced packaging
Make chip packaging more reliable
Emerging applications and challenges of packaging
Name* (Note: This name will be displayed publicly)
Email* (this will not be displayed publicly)
Some market segments are normalizing, and other market segments may be affected in 2022.
Threats are growing and expanding, but what is considered sufficient may vary by application or user. Even so, it may not be enough.
Large-scale expansion campaigns target various chips, but export controls limit the growth of the lead.
How doping atoms make qubits last longer.
The CTO of JCET talked about the slowdown in Moore's Law and the growing interest in new packaging methods and small chips.
With the development of SiC to higher voltages, BEV users can get faster charging, longer cruising range and lower system costs
Some market segments are normalizing, and other market segments may be affected in 2022.
Imec's senior vice president delves into GAA FETs, interconnects, chiplets and 3D packaging.
Five process nodes in four years, high NA EUV, 3D-IC, small chip, hybrid bonding, etc.
Threats are growing and expanding, but what is considered sufficient may vary by application or user. Even so, it may not be enough.
Abstraction is the key to custom processor design and verification, but defining the correct language and tool flow is a work in progress.
Large-scale expansion campaigns target various chips, but export controls limit the growth of the lead.
New and faster memory designs are being developed, but their future is uncertain.